View CY14E064L-SZ35XIT_4077836.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy14e064l 64 kbit (8k x 8) nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-06543 rev. *e revised apr 18, 2008 features 25 ns and 45 ns access times hands off automatic store on power down with external 68 mf capacitor store to quantumtrap? nonvolatile elements is initiated by software, hardware, or autostore? on power down recall to sram initiated by software or power up unlimited read, write and recall cycles 10 ma typical icc at 200 ns cycle time 1,000,000 store cycl es to quantumtrap 100 year data retention to quantumtrap single 5v operation +10% commercial temperature soic package rohs compliance functional description the cypress cy14e064l is a fast static ram with a nonvol- atile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolat ile memory. the sram provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. a hardware store is initiated with the hsb pin. store/ recall control power control software detect static ram array 128 x 512 quantum trap 128 x 512 store recall column i/o column dec row decoder input buffers oe ce we hsb v cc v cap a 0 - a 12 a 0 a 1 a 2 a 3 a 4 a 10 a 5 a 6 a 7 a 8 a 9 a 11 a 12 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 logic block diagram [+] feedback
cy14e064l document number: 001-06543 rev. *e page 2 of 17 pin configurations pin definitions pin name io type description a 0 ?a 12 input address inputs. used to select one of the 8,192 bytes of the nvsram. dq0-dq7 input or output bidirectional data io lines . used as input or output lines depending on operation. we input write enable input, active low . when selected low, writes data on the io pins to the address location latched by the falling edge of ce . ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the io pins to tri-state. v ss ground ground for the device . the device is connected to ground of the system. v cc power supply power supply inputs to the device . hsb input or output hardware store busy (hsb) . when low, this output indicates a hardware store is in progress. when pulled low external to the chip, it initiates a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). v cap power supply autostore capacitor . supplies power to nvsram during power loss to store data from sram to nonvolatile elements. v cap a 12 a 7 a 6 a 5 a 4 v cc hsb we a 8 a 9 a 11 oe a 10 dq6 dq7 dq5 ce dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v ss dq0 a 3 a 2 a 1 a 0 dq1 dq2 28-soic top view (not to scale) [+] feedback
cy14e064l document number: 001-06543 rev. *e page 3 of 17 device operation the cy14e064l nvsram is made up of two functional compo- nents paired in the same physical cell. these are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the store operation) or from the nonvolatile cell to sram (the recall operation). this unique arch itecture enables the storage and recall of all cells in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14e064l supports unlimited reads and writes similar to a typical sram. in addition, it provides unlimited recall opera- tions from the nonvolatile cells and up to one million store operations. sram read the cy14e064l performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0?12 determines the 8,192 data bytes accessed. when the read is initiated by an ad dress transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs are stable prior to entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. the data on the common io pins i/o 0?7 are written into the memory if it is valid t sd , before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entire write cycle to avoid data bus contention on common io lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14e064l stores data to nvsram using one of three storage operations: 1. hardware store activated by hsb 2. software store activated by an address sequence 3. autostore on device power down autostore operation is a uni que feature of quantumtrap technology and is enabled by default on the cy14e064l. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 1 shows the proper connection of the storage capacitor (v cap ) for automatic store ope ration. refer to the dc electrical characteristics on page 7 for the size of v cap . the voltage on the v cap pin is driven to 5v by a charge pump internal to the chip. a pull up is placed on we to hold it inactive during power up. figure 1. autostore mode 28 1 10k ohm 68 f u 6v, +20% 10k ohm 27 26 14 15 0.1 f u bypass [+] feedback
cy14e064l document number: 001-06543 rev. *e page 4 of 17 in system power mode, both v cc and v cap are connected to the +5v power supply without the 68 f capacitor. in this mode, the autostore function of the cy14e064l operates on the stored system charge as power goes down. the user must, however, guarantee that v cc does not drop below 3.6v during the 10 ms store cycle. if an automatic store on power loss is not required, then v cc is tied to ground and + 5v is applied to v cap ( figure 2 ). this is the autostore inhibit mode, where the autostore function is disabled. if the cy14e064l is op erated in this configuration, references to v cc are changed to v cap throughout this data sheet. in this mode, store operations are triggered through software control or the hsb pin. it is not permissible to change between these three options at will. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored, unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. the hsb signal is monitored by the system to de tect if an autostore cycle is in progress. hardware store (hsb ) operation the cy14e064l provides the hsb pin for controlling and acknowledging the store operations. the hsb pin is used to request a hardware st ore cycle. when the hsb pin is driven low, the cy14e064l conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram takes place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition, while the store (initiated by any means) is in progress. sram read and write operations, that are in progress when hsb is driven low by any means, are given time to complete before the store operation is initiated. after hsb goes low, the cy14e064l cont inues sram operations for t delay . during t delay , multiple sram read operations take place. if a write is in progress when hsb is pulled low, it allows a time, t delay to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. the hsb pin is used to synchronize multiple cy14e064l while using a single larger capacitor. to operate in this mode, the hsb pin is connected together to the hsb pins from the other cy14e064l. an external pull up resistor to +5v is required, since hsb acts as an open drain pull down. the v cap pins from the other cy14e064l parts are tied together and share a single capacitor. the capacitor size is scaled by the number of devices connected to it. when any one of the cy14e064l detects a power loss and asserts hsb , the common hsb pin causes all parts to request a store cycle. (a store takes place in those cy14e064l that are written since the last nonvolatile cycle.) during any store operation, regardless of how it is initiated, the cy14e064l continues to drive the hsb pin low, releasing it only when the store is complete. after completing the store operation, the cy14e064l remains disabled until the hsb pin returns high. if hsb is not used, it is left unconnected. hardware recall (power up) during power up or after any low power condition (v cc < v switch ), an internal recall request is latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle is automatically initiated and takes t hrecall to complete. if the cy14e064l is in a write state at the end of power up recall, the sram data is corrupted. to help avoid this situation, a 10 kohm resistor is connected either between we and system v cc or between ce and system v cc . software store using a software address sequence, transfer the data from the sram to the nonvolatile memory. the cy14e064l software store cycle is initiated by executing sequential ce controlled read cycles from six specific address locations in exact order. during the store cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. when a st ore cycle is initiated, further input and output ar e disabled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence. if they intervene, the sequence is aborted and no store or recall takes place. to initiate the software store cycle, the following read sequence is performed: 1. read address 0x0000, valid read 2. read address 0x1555, valid read 3. read address 0x0aaa, valid read 4. read address 0x1fff, valid read 5. read address 0x10f0, valid read 6. read address 0x0f0f, initiate store cycle the software sequence is clocked with ce controlled reads or oe controlled reads. when the sixth address in the sequence is entered , the store cycle commences and the chip is disabled. it is important that read cycles and not figure 2. autostore inhibit mode 28 1 10k ohm 10k ohm 27 26 14 15 0.1 f u bypass [+] feedback
cy14e064l document number: 001-06543 rev. *e page 5 of 17 write cycles are used in the s equence. it is not necessary that oe is low for a valid sequence. after the t store cycle time is fulfilled, the sram is again activated for read and write operation. software recall data is transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations is performed: 1. read address 0x0000, valid read 2. read address 0x1555, valid read 3. read address 0x0aaa, valid read 4. read address 0x1fff, valid read 5. read address 0x10f0, valid read 6. read address 0x0f0e, initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared, and then the nonvolatile information is transferred into the sram cells. after the t recall cycle time, the sram is once again ready for read and write operations. the recall operation does not alter the data in the nonvolatile elements. data protection the cy14e064l protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc is less than v switch . if the cy14e064l is in a write mode (both ce and we are low) at power up after a recall or after a store, the write is inhibited until a negative transition on ce or we is detected. this protects against inadvertent writes during power up or brown out conditions. noise considerations the cy14e064l is a high speed memory. it must have a high frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss, using leads and traces that are as short as possible. as with all high speed cmos ics, careful routing of power, ground, and signals reduce circuit noise. low average active power cmos technology provides the cy14e064l the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. figure 3 shows the relationship between i cc and read or write cycle time. wors t case current consumption is shown for both cmos and ttl input levels (commercial temper- ature range, vcc = 5.5v, 100% duty cycle on chip enable). only standby current is drawn when the chip is disabled. the overall average current drawn by the cy14e064l depends on the following items: 1. the duty cycle of chip enable 2. the overall cycle rate for accesses 3. the ratio of reads to writes 4. cmos versus ttl input levels 5. the operating temperature 6. the v cc level 7. io loading figure 3. current ve rsus cycle time (read) figure 4. current vers us cycle time (write) [+] feedback
cy14e064l document number: 001-06543 rev. *e page 6 of 17 preventing stores the store function is disabled by holding hsb high with a driver capable of sourcing 30 ma at a v oh of at least 2.2v, because it has to overpower the internal pull down device. this device drives hsb low for 20 s at the onset of a store. when the cy14e064l is connec ted for autostore operation (system v cc connected to v cc and a 68 f capacitor on v cap ) and v cc crosses v switch on the way down, the cy14e064l attempts to pull hsb low. if hsb does not actually get below v il , the part stops trying to pull hsb low and abort the store attempt. table 1. hardware mode selection ce we hsb a12?a0 mode io power h x h x not selected output high z standby l h h x read sram output data active l l h x write sram input data active x x l x nonvolatile store output high z i cc2 l h h 0000 1555 0aaa 1fff 10f0 0f0f read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 l h h 0000 1555 0aaa 1fff 10f0 0f0e read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [+] feedback
cy14e064l document number: 001-06543 rev. *e page 7 of 17 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied ............................................ ?55 c to +125 c supply voltage on v cc relative to gnd ..........?0.5v to 7.0v voltage applied to outputs in high z state ....................................... ?0.5v to v cc + 0.5v input voltage.............................................?0.5v to vcc+0.5v transient voltage (<20 ns) on any pin to ground potentia l ............ ...... ?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount lead soldering temperature (3 seconds) .......................................... +260 c output short circuit current [1] .................................... 15 ma static discharge voltage....... ........... ............ ............ > 2001v (mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 4.5v to 5.5v dc electrical characteristics over the operating range (v cc = 4.5v to 5.5v) [2] parameter description test conditions min max unit i cc1 average v cc current t rc = 25 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. commercial 85 65 ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store 3ma i cc3 average v cc current at t avav = 200 ns, 5v, 25c typical we > (v cc ? 0.2). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. 10 ma i cc4 average v cap current during autostore cycle all inputs do not care, v cc = max average current for duration t store 2ma i sb v cc standby current ce > (v cc ? 0.2). all others v in < 0.2v or > (v cc ? 0.2v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0mhz. 2.5 ma i ix input leakage current v cc = max, v ss < v in < v cc -1 +1 a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih -5 +5 a v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v notes 1. outputs shorted for no more than one second. no more than one output shorted at a time. 2. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperat ure) and v cc = 5v. not 100% tested. [+] feedback
cy14e064l document number: 001-06543 rev. *e page 8 of 17 capacitance these parameters are guaranteed but not tested. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0 v 8pf c out output capacitance 7 pf thermal resistance [ these parameters are guaranteed but not tested. parameter description test conditions 28-soic unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. tbd c/w jc thermal resistance (junction to case) tbd c/w ac test loads ac test conditions 5.0v output 30 pf r1 963w r2 512 5.0v output 5 pf r1 963 r2 512 for tri-state specs input pulse levels .................................................. 0 v to 3 v input rise and fall times (10% - 90%)........................ < 5 ns input and output timing referenc e levels ......... .......... 1.5 v [+] feedback
cy14e064l document number: 001-06543 rev. *e page 9 of 17 ac switching characteristics parameter description 25 ns part 45 ns part unit min max min max cypress parameter alt sram read cycle t ace t acs chip enable access time 25 45 ns t rc [4] t rc read cycle time 25 45 ns t aa [5] t aa address access time 25 45 ns t doe t oe output enable to data valid 10 20 ns t oha [5] t oh output hold after address change 5 5 ns t lzce [6] t lz chip enable to output active 5 5 ns t hzce [6] t hz chip disable to output inactive 10 12 ns t lzoe [6] t olz output enable to output active 0 0 ns t hzoe [6] t ohz output disable to output inactive 10 12 ns t pu [3] t pa chip enable to power active 0 0 ns t pd [3] t ps chip disable to power standby 25 45 ns sram write cycle t wc t wc write cycle time 25 45 ns t pwe t wp write pulse width 20 30 ns t sce t cw chip enable to end of write 20 30 ns t sd t dw data setup to end of write 10 15 ns t hd t dh data hold after end of write 0 0 ns t aw t aw address setup to end of write 20 30 ns t sa t as address setup to start of write 0 0 ns t ha t wr address hold after end of write 0 0 ns t hzwe [6,7] t wz write enable to output disable 10 14 ns t lzwe [6] t ow output active after end of write 5 5 ns autostore or power up recall parameter description cy14e064l unit min max t hrecall [8] power up recall duration 550 s t store [9] store cycle duration 10 ms v switch low voltage trigger level 4.0 4.5 v t vccrise v cc rise time 150 s notes 3. these parameters are guaranteed but not tested. 4. we must be high during sram read cycles. 5. device is continuously selected with ce and oe both low. 6. measured 200 mv from steady state output voltage. 7. if we is low when ce goes low, the outputs remain in the high impedance state. 8. t hrecall starts from the time v cc rises above v switch . 9. if an sram write does not take place since the last nonvolatile cycle, no store takes place. [+] feedback
cy14e064l document number: 001-06543 rev. *e page 10 of 17 software controlled store/recall cycle the software controlled store/recall cycle follows. [10,11] parameter description 25 ns part 45 ns part unit min max min max t rc store/recall initiation cycle time 25 45 ns t as address setup time 0 0 ns t cw clock pulse width 20 30 ns t glax address hold time 20 20 ns t recall recall duration 20 20 s hardware store cycle parameter description cy14e064l unit min max t store [6] store cycle duration 10 ms t delay [12] time allowed to co mplete sram cycle 1 s t restore [13] hardware store high to inhibit off 700 ns t hlhx hardware store pulse width 15 ns t hlbl hardware store low to store busy 300 ns notes 10. the software sequence is clocked with ce controlled reads. 11. the six consecutive addresses must be read in the order listed in the mode selection table. we must be high during all six consecutive cycles. 12. read and write cycles in progress before hsb are given this amount of time to complete. 13. t restore is only applicable after t store is complete. [+] feedback
cy14e064l document number: 001-06543 rev. *e page 11 of 17 switching waveforms figure 5. sram read cy cle 1: address controlled [4, 5, 14] figure 6. sram read cycle 2: ce controlled [4,14] t rc t aa t oh address dq (data out) data valid address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe t hzoe data valid active standby t pu dq (data out) icc note 14. hsb must remain high during read and write cycles. [+] feedback
cy14e064l document number: 001-06543 rev. *e page 12 of 17 switching waveforms (continued) t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data figure 7. sram write cycle 1: we controlled [14,15] note 15. ce or we must be greater than v ih during address transitions. t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data valid figure 8. sram write cycle 2: ce controlled [+] feedback
cy14e064l document number: 001-06543 rev. *e page 13 of 17 switching waveforms (continued) v cc v switch t restore autostore power-up recall v reset t store t delay t vsbl hsb dq (data out) power up recall brown out no stroke (no sram writes) no recall (v cc did not go below v reset ) brown out autostore no recall (v cc did not go below v reset ) tm brown out autostore tm recall when v cc returns above vswitch figure 9. autost ore/power up recall [+] feedback
cy14e064l document number: 001-06543 rev. *e page 14 of 17 switching waveforms (continued) t rc t rc t sa t sce t glax t store / t recall data valid data valid address # 1 address # 6 high impedance address ce oe dq (data) a a a a a a a a a a a a a a figure 10. ce controlled software store/recall cycle [9] t hlhx t store t hlbl t delay data valid data valid high impedance high impedance hsb (in) dq (data out) hsb (out) a a a a a a figure 11. hardware store cycle [+] feedback
cy14e064l document number: 001-06543 rev. *e page 15 of 17 option: t-tape and reel blank - std. speed: 25 - 25 ns 45 - 45 ns package: sz - 28-soic data bus: l - x8 density: 064 - 64 kb voltage: cypress part numbering nomenclature cy 14 e 064 l- sz 25 x c t e - 5.0v nvsram 14 - autostore + software store + hardware store temperature: c - commercial (0 to 70c) pb-free [+] feedback
cy14e064l document number: 001-06543 rev. *e page 16 of 17 ordering information speed (ns) ordering code package diagram package type operating range 25 cy14e064l-sz25xct 001-10395 28-pin soic (pb-free) commercial cy14e064l-sz25xc 001-10395 28-pin soic (pb-free) 25 cy14e064l-sz25xit 001-10395 28-pin soic (pb-free) industrial cy14e064l-sz25xi 001-10395 28-pin soic (pb-free) 35 cy14e064l-sz35xct 001-10395 28-pin soic (pb-free) commercial cy14e064l-sz35xc 001-10395 28-pin soic (pb-free) 35 CY14E064L-SZ35XIT 001-10395 28-pi n soic (pb-free) industrial cy14e064l-sz35xi 001-10395 28-pin soic (pb-free) 45 cy14e064l-sz45xct 001-10395 28-pin soic (pb-free) commercial cy14e064l-sz45xc 001-10395 28-pin soic (pb-free) 45 cy14e064l-sz45xit 001-10395 28-pi n soic (pb-free) industrial cy14e064l-sz45xi 001-10395 28-pin soic (pb-free) package diagrams 28-pin (350 mil) soic(001-10395) 001-10395-** [+] feedback
document number: 001-06543 rev. *e revised apr 18, 2008 page 17 of 17 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i 2 c components from cypress or one of its sublicense d associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. autostore and quantumtrap are registered trademarks of simtek corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy14e064l ? cypress semiconductor corporation, 2006-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy14e064l 64 kbit (8k x 8) nvsram document number: 001-06543 rev. ecn no. issue date orig. of change description of change ** 427789 see ecn tup new data sheet *a 437321 see ecn tup show data sheet on web *b 472053 see ecn tup removed 55 ns speed option updated part numbering nomenclature and ordering information *c 503290 see ecn pci changed from advance to preliminary changed the term ?unlimited? to ?infinite? removed industrial grade mention removed 35 ns speed bin removed icc1 values from the dc table for 35 ns industrial grade corrected v il min specification from (v cc - 0.5) to (v ss - 0.5) removed all references pertaining to oe controlled software store and recall operation included package diagram for 28-pin (350 mil) soic updated ?part nomenclature table? and ?ordering information table? *d 1349963 see ecn uha/sfv changed from preliminary to final updated ac test conditions updated ordering information table *e 2427986 see ecn gvch move to external web [+] feedback

▲Up To Search▲

Price & Availability of CY14E064L-SZ35XIT

	To Download CY14E064L-SZ35XIT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .